1. Overview
Memory banks defined in DALI2 standard are supported. Besides, additional manufacturer extended memory banks are defined.
2. Terms and Definitions
Name | Description |
NC | No Change |
NA | Not Applicable |
NO | No Answer |
DFT | Factory burn-in default value |
ACT | Actual situation |
NVM/RAM-RO | NVM/RAM read only |
NVM/RAM | NVM/RAM readable and writable |
NVM/RAM-XX-P | Protected NVM/RAM |
3. Data Protection
Parameters can be protected by OEM Key. Once this feature is enabled, user would need to firstly write OEM Key into Memory Bank 10 related OEM Key locations. If key is
correct, all related parameters will be unprotected and then can be modified.
We support 2 keys, Master Key and User Key. For all User Key protected features, Master Key can also unprotect them. But for Master Key protected parameters, User Key can not unprotect them.
By default Master Key and User Key are empty(0xFF..FF), then all parameters are not protected, until writing in new keys. If user wants protection, Master Key is mandatory to write in. If Master Key is empty, User Key will not work, and driver will work as No Protect.
If user wants to change Master Key, user needs to firstly write in Master Key to unprotect, and then write new keys to related key locations. If user wants to change User Key, user needs to firstly write in Master Key or User Key to unprotect, and then write new keys to related key locations. Remind if user forgets Master Key, he will not be able to delete/change it any more!!!
4. Memory Banks
For multi bytes parameter, lower address is MSB.
4.1 Memory Bank 0
This memory bank follows DALI standard 102, without including additional gear information.
Address | Description | Default value | Memory type |
0x00 | address of last accessible memory location | 0x96 | ROM |
0x01 | Reserved – not implemented | NO | NA |
0x02 | number of last accessible memory bank | DFT | ROM |
0x03-0x08 | GTIN | DFT | ROM |
0x09 | firmware version (major) | DFT | ROM |
0x0A | firmware version (minor) | DFT | ROM |
0x0B-0x12 | identification number byte(1) | DFT | NVM |
0x13 | hardware version (major)(1) | DFT | NVM |
0x14 | hardware version (minor)(1) | DFT | NVM |
0x15 | 101 version number | 0x08(2.0) | ROM |
0x16 | 102 version number of all integrated control gear | 0x08(2.0) | ROM |
0x17 | 103 version number of all integrated control devices | 0xFF | ROM |
0x18 | number of logical control device units in the bus unit | 0 | ROM |
0x19 | number of logical control gear units in the bus unit | DFT | ROM |
0x1A | index number of this logical control gear unit | 0 | ROM |
0x1B-0x7F | Reserved – not implemented | NO | NA |
0x80-0x81 | Firmware Build Ver | DFT | ROM |
0x82-0x83 | Bootloader Ver | DFT | ROM |
0x84-0x95 | Reserved | DFT | ROM |
0xA0-0xA3 | Article Number | DFT | NVM |
0xA4 | Production Year | DFT | NVM |
0xA5 | Production Week | DFT | NVM |
4.2 Memory Bank 1(OEM Data)
This memory bank follows DALI standard 102 and 251
Address | Description | Default value | Reset value | Memory type |
0x00 | Address of last addressable memory location | 0xFE | NC | ROM |
0x01 | Indicator byte | NO | NO | NA |
0x02 | Lock byte | 0xFF | 0xFF | RAM |
0x03-0x08 | Luminaire manufacturer GTIN | 0xFF | NC | NVM-P |
0x09-0x10 | Luminaire identification number | 0xFF | NC | NVM-P |
0x11 | Content Format ID (MSB) | 0x00 | NC | NVM-P |
0x12 | Content Format ID (LSB) | 0x03 | NC | NVM-P |
0x13 | Luminaire year of manufacture [YY] | 0xFF | NC | NVM-P |
0x14 | Luminaire week of manufacture [WW] | 0xFF | NC | NVM-P |
0x15-0x16 | Nominal Input Power [W] | 0xFF | NC | NVM-P |
0x17-0x18 | Power at minimum dim level [W] | 0xFF | NC | NVM-P |
0x19-1A | Nominal Minimum AC mains voltage [V] | 0xFF | NC | NVM-P |
0x1B-0x1C | Nominal Maximum AC mains voltage [V] | 0xFF | NC | NVM-P |
0x1D-0x1F | Nominal light output [Lm] | 0xFF | NC | NVM-P |
0x20 | CRI | 0xFF | NC | NVM-P |
0x21-0x22 | CCT [K] | 0xFF | NC | NVM-P |
0x23 | Light Distribution Type | 0xFF | NC | NVM-P |
0x24-0x3B | Luminaire color | 0x00 | NC | NVM-P |
0x3C-0x77 | Luminaire identification | 0x00 | NC | NVM-P |
0x78-0xFE | Manufacturer-specific. | 0x00 | NC | NVM-P |
4.3 Memory Bank 2(Push)
Address | Description | Default value | Reset value | Memory type |
0x00 | Address of last addressable memory location | 0x0D | NC | ROM |
0x01 | Reserved – not implemented | NO | NA | NA |
0x02 | Lock byte | 0xFF | 0xFF | RAM |
0x03 | Version of the memory bank | 0x02 | NC | ROM |
0x04 | Push Configure | DFT | NC | NVM-P |
0x05 | Push Stored Level | 0xFF | NC | NVM-P |
0x06-0x07 | Push Stored CCT | 0xFFFF | NC | NVM-P |
0x08 | Corridor Operate Level | 0xFF | NC | NVM-P |
0x09 | Corridor Standby Level | 0xFF | NC | NVM-P |
0x0A | Corridor Fade In Time | 0xFF | NC | NVM-P |
0x0B | Corridor Hold On Time | 0xFF | NC | NVM-P |
0x0C | Corridor Fade Out Time | 0xFF | NC | NVM-P |
0x0D | Corridor Switch Off Time | 0xFF | NC | NVM-P |
4.4 Memory Bank 3(CLO)
Address | Description | Default value | Reset value | Memory type |
0x00 | Address of last addressable memory location | 0x14 | NC | ROM |
0x01 | Reserved – not implemented | NO | NA | NA |
0x02 | Lock byte | 0xFF | 0xFF | RAM |
0x03 | Version of the memory bank | 0x02 | NC | ROM |
0x04-0x05 | Luminare Operating Time | DFT | NC | NVM-P |
0x06 | CLO Intensity0 | 0xFF | NC | NVM-P |
0x07 | CLO Time1 | 0xFF | NC | NVM-P |
0x08 | CLO Intensity1 | 0xFF | NC | NVM-P |
0x09 | CLO Time2 | 0xFF | NC | NVM-P |
0x0A | CLO Intensity2 | 0xFF | NC | NVM-P |
0x0B | CLO Time3 | 0xFF | NC | NVM-P |
0x0C | CLO Intensity3 | 0xFF | NC | NVM-P |
0x0D | CLO Time4 | 0xFF | NC | NVM-P |
0x0E | CLO Intensity4 | 0xFF | NC | NVM-P |
0x0F | CLO Time5 | 0xFF | NC | NVM-P |
0x10 | CLO Intensity5 | 0xFF | NC | NVM-P |
0x11 | CLO Time6 | 0xFF | NC | NVM-P |
0x12 | CLO Intensity6 | 0xFF | NC | NVM-P |
0x13 | CLO Time7 | 0xFF | NC | NVM-P |
0x14 | CLO Intensity7 | 0xFF | NC | NVM-P |
4.5 Memory Bank 4(Gear)
Address | Description | Default value | Reset value | Memory type |
0x00 | Address of last addressable memory location | 0x18 | NC | ROM |
0x01 | Reserved – not implemented | NO | NA | NA |
0x02 | Lock byte | 0xFF | 0xFF | RAM |
0x03 | Version of the memory bank | 0x02 | NC | ROM |
0x04 | Channel Mode | DFT | NC | NVM-P |
0x05-0x06 | Current Set | DFT | NC | NVM-P |
0x07-0x08 | CH2 Current Set | DFT | NC | NVM-P |
0x09 | OTP Configure | DFT | NC | NVM-P |
0x0A | OTP Internal Temperature Offset | 0 | NC | NVM-P |
0x0B | OTP Start Derate Temperature | DFT | NC | NVM-P |
0x0C | OTP Stop Derate Temperature | DFT | NC | NVM-P |
0x0D | OTP Shutdown Temperature | DFT | NC | NVM-P |
0x0E | OTP Derate Intensity | DFT | NC | NVM-P |
0x0F | OTP Shutdown Intensity | DFT | NC | NVM-P |
0x10 | Emergency Configure | 1 | NC | NVM-P |
0x11 | Emergency Level | 185 | NC | NVM-P |
0x12-0x13 | Emergency CCT | 0xFFFF | NC | NVM-P |
0x14 | Power On Fade Time | 0xFF | NC | NVM-P |
0x15-0x16 | Current Max Limit | DFT | NC | NVM-P |
0x17-0x18 | Current Min Limit | DFT | NC | NVM-P |
4.6 Memory Bank 5(Color LED)
Address | Description | Default value | Reset value | Memory type |
0x00 | Address of last addressable memory location | 0x0F | NC | ROM |
0x01 | Reserved – not implemented | NO | NA | NA |
0x02 | Lock byte | 0xFF | 0xFF | RAM |
0x03 | Version of the memory bank | 0x01 | NC | ROM |
0x04-0x05 | CH1 LED Flux | 0xFFFF | NC | NVM-P |
0x06-0x07 | CH1 LED Color Coordinate X | 0xFFFF | NC | NVM-P |
0x08-0x09 | CH1 LED Color Coordinate Y | 0xFFFF | NC | NVM-P |
0x0A-0x0B | CH2 LED Flux | 0xFFFF | NC | NVM-P |
0x0C-0x0D | CH2 LED Color Coordinate X | 0xFFFF | NC | NVM-P |
0x0E-0x0F | CH2 LED Color Coordinate Y | 0xFFFF | NC | NVM-P |
4.7 Memory Bank 10(General Parameters)
Address | Description | Default value | Reset value | Memory type |
0x00 | Address of last addressable memory location | 0x5F | NC | ROM |
0x01 | Reserved – not implemented | NO | NA | NA |
0x02 | Lock byte | 0xFF | 0xFF | RAM |
0x03 | Version of the memory bank | 0x0C | NC | ROM |
0x04-0x07 | Command | RAM | NC | RAM-P |
0x08 | Protect Status | 0x00 | 0x00 | RAM |
0x09-0x0B | Protect Features | 0x00 | NC | NVM-P |
0x0C-0x0F | Reserved | 0x00 | NC | ROM |
0x10-0x1F | OEM Master Key | 0xFF..FF | NC | RAM-P |
0x20-0x2F | OEM User Key | 0xFF..FF | NC | RAM-P |
0x30-0x3F | Production Key | 0xFF..FF | NC | RAM-P |
0x40-0x43 | Article No | 0xFF..FF | NC | NVM-P |
0x44 | Production Year | 0xFF | NC | NVM-P |
0x45 | Production Week | 0xFF | NC | NVM-P |
0x46-0x4F | Additional Gear Info | 0xFF..FF | NC | NVM-P |
0x50-0x55 | GTIN | 0xFF..FF | NC | NVM-P |
0x56-0x5D | Identification number | 0xFF..FF | NC | NVM-P |
0x5E-0x5F | Hardware Ver | 0xFFFF | NC | NVM-P |
Command: The command will take effective when Byte3(LSB) is written.
Command | Byte0 | Byte1 | Byte2 | Byte3 |
Update Master Key | 0x83 | 0x00 | 0xAA | 0xAA |
Update User Key | 0x83 | 0x01 | 0xAA | 0xAA |
Restore To Factory Default | 0x82 | 0xAA | 0xAA | 0xAA |
Enter CLO Test Mode | 0xA0 | 0x10 | 0x00 | 0x00 |
Enter Production Mode | 0xA1 | 0x00 | 0xAA | 0xAA |
Enter CLO Test Mode: CLO Operating Time will be accelated to 1Kh per sec. After power cycle, test mode will exit.
Protect Status:
Bit7-4 | Bit3 | Bit2 | Bit1 | Bit0 |
Reserved | UKS | UKPT | MKS | MKPT |
MKPT: Master Key Protected.
-
0: Not Protected
- 1: Protected
UKPT: User Key Protected.
-
0: Not Protected
- 1: Protected
MKS: Master Key Set.
-
0: Not Set
- 1: Already Set
UKS: User Key Set.
-
0: Not Set
- 1: Already Set
Protect Features: Features to be protected by current OEM User Key. 0x00 is no features protected.
Bit14-15 | Bit12-13 | Bit10-11 | Bit8-9 | Bit6-7 | Bit4-5 | Bit2-3 | Bit0-1 |
Color LED | Push | Dali253 | OEM Data | OTP | Emergency | CLO | ISET |
-
0: Not Protected
- 1: Master key and user key protected
- 2: Master key protected
- 3: Reserved
OEM Master Key: If Master Key is not Set, write into correct master key will unprotect the features. Write into LSB byte will take effective. Firstly writing into new key, and then write Update OEM Master Key command will change password.
OEM User Key: If User Key is not Set, write into correct master key will unprotect the features. Write into LSB byte will take effective. Firstly writing into new key, and then write Update OEM User Key command will change password.
Hardware Ver: After the bytes changed, related value in Memory Bank 0 will be updated accordingly
GTIN: After the bytes changed, related value in Memory Bank 0 will be updated accordingly
Identification number: After the bytes changed, related value in Memory Bank 0 will be updated accordingly
4.8 Memory Bank 11(Calibration)
Address | Description | Default value | Reset value | Memory type |
0x00 | Address of last addressable memory location | 0x3F | NC | ROM |
0x01 | Reserved – not implemented | NO | NA | NA |
0x02 | Lock byte | 0xFF | 0xFF | RAM |
0x03 | Version of the memory bank | 0x04 | NC | ROM |
0x04 | RX Low Bit Actual Offset | NC | RAM-RO-P | |
0x05 | RX High Bit Actual Offset | NC | RAM-RO-P | |
0x06 | RX Low Bit Self Check Actual Offset | NC | RAM-RO-P | |
0x07 | RX High Bit Self Check Actual Offset | NC | RAM-RO-P | |
0x08 | TX Low Bit Calibrated Offset | 0 | NC | NVM-P |
0x09 | TX High Bit Calibrated Offset | 0 | NC | NVM-P |
0x0A | RX Low Bit Calibrated Offset | 0 | NC | NVM-P |
0x0B | RX High Bit Calibrated Offset | 0 | NC | NVM-P |
0x10-0x1F | Customized Calibration Bytes | 0 | NC | NVM-P |
4.9 Memory Bank 201(Integrated Bus Power Supply)
This memory bank follows DALI standard 250
Address | Description | Default value | Reset value | Memory type |
0x00 | Address of last addressable memory location | 0x06 | NC | ROM |
0x01 | Indicator byte | NO | NO | NA |
0x02 | Lock byte | 0xFF | 0xFF | RAM |
0x03 | Version of the memory bank | 0x01 | NC | ROM |
0x04 | Guaranteed supply current of integrated DALI bus power supply | 0xFF | NC | ROM |
0x05 | Maximum supply current of integrated DALI bus power supply | 0x00 | NC | ROM |
0x06 | DALI bus power supply status | 0x03 | NC | NVM-P |
4.10 Memory Bank 202(active energy and power)
This memory bank follows DALI standard 252
Address | Description | Default value | Reset value | Memory type |
0x00 | Address of last addressable memory location | 0x0F | NC | ROM |
0x01 | Indicator byte | NO | NO | NA |
0x02 | Lock byte | 0xFF | 0xFF | RAM |
0x03 | Version of the memory bank | 0x01 | NC | ROM |
0x04 | ScaleFactorForActiveEnergy | 0xFE(0.01W) | NC | ROM |
0x05-0x0A | ActiveEnergy | 0x00 | NC | NVM-RO |
0x0B | ScaleFactorForActivePower | 0xFE(0.01W) | NC | ROM |
0x0C-0x0F | ActivePower | 0x00 | NC | RAM-RO |
4.11 Memory Bank 205(control gear diagnostics and maintenance)
This memory bank follows DALI standard 253
Address | Description | Default value | Reset value | Memory type |
0x00 | Address of last addressable memory location | 0x1C | NC | ROM |
0x01 | Reserved – not implemented | NO | NA | NA |
0x02 | Lock byte | 0xFF | 0xFF | RAM |
0x03 | Version of the memory bank | 0x01 | NC | ROM |
0x04-0x07 | ControlGearOperatingTime | 0x00 | NC | NVM-RO |
0x08-0x0A | ControlGearStartCounter | 0x00 | NC | NVM-RO |
0x0B-0x0C | ControlGearExternalSupplyVoltage(1) | 0xFF | NC | ROM |
0x0D | ControlGearExternalSupplyVoltageFrequency(1) | 0xFF | NC | ROM |
0X0E | ControlGearPowerFactor(1) | 0xFF | NC | ROM |
0x0F | ControlGearOverallFailureCondition | ACT | NC | RAM-RO |
0x10 | ControlGearOverallFailureConditionCounter | 0x00 | 0x00 | NVM-RO |
0x11 | ControlGearExternalSupplyUndervoltage(1) | 0xFF | NC | ROM-P |
0x12 | ControlGearExternalSupplyUndervoltageCounter | 0x00 | 0x00 | NVM-RO-P |
0x13 | ControlGearExternalSupplyOvervoltage(1) | 0xFF | NC | ROM-P |
0x14 | ControlGearExternalSupplyOvervoltageCounter | 0x00 | 0x00 | NVM-RO-P |
0x15 | ControlGearOutputPowerLimitation(1) | 0xFF | NC | ROM-P |
0x16 | ControlGearOutputPowerLimitationCounter | 0x00 | 0x00 | NVM-RO-P |
0x17 | ControlGearThermalDerating | ACT | NC | RAM-RO-P |
0x18 | ControlGearThermalDeratingCounter | 0x00 | 0x00 | NVM-RO-P |
0x19 | ControlGearThermalShutdown | ACT | NC | RAM-RO-P |
0x1A | ControlGearThermalShutdownCounter | 0x00 | 0x00 | NVM-RO-P |
0x1B | ControlGearTemperature | ACT | NC | RAM-RO |
0x1C | ControlGearOutputCurrentPercent | ACT | NC | RAM-RO |
4.12 Memory Bank 206(light source diagnostics and maintenance)
This memory bank follows DALI standard 253
Address | Description | Default value | Reset value | Memory type |
0x00 | Address of last addressable memory location | 0x20 | NC | ROM |
0x01 | Reserved – not implemented | NO | NA | NA |
0x02 | Lock byte | 0xFF | 0xFF | RAM |
0x03 | Version of the memory bank | 0x01 | NC | ROM |
0x04-0x06 | LightSourceStartCounterResettable | 0x00 | NC | NVM |
0x07-0x09 | LightSourceStartCounter | 0x00 | NC | NVM-RO |
0x0A-0x0D | LightSourceOnTimeResettable | 0x00 | NC | NVM |
0x0E-0x11 | LightSourceOnTime | 0x00 | NC | NVM-RO |
0x12-0x13 | LightSourceVoltage | ACT | NC | RAM-RO |
0x14-0x15 | LightSourceCurrent | ACT | NC | RAM-RO |
0x16 | LightSourceOverallFailureCondition | ACT | NC | RAM-RO |
0x17 | LightSourceOverallFailureConditionCounter | 0x00 | 0x00 | NVM-RO |
0x18 | LightSourceShortCircuit | ACT | NC | RAM-RO-P |
0x19 | LightSourceShortCircuitCounter | 0x00 | 0x00 | NVM-RO-P |
0x1A | LightSourceOpenCircuit | ACT | NC | RAM-RO-P |
0x1B | LightSourceOpenCircuitCounter | 0x00 | 0x00 | NVM-RO-P |
0x1C | LightSourceThermalDerating | ACT | NC | RAM-RO-P |
0x1D | LightSourceThermalDeratingCounter | 0x00 | 0x00 | NVM-RO-P |
0x1E | LightSourceThermalShutdown | ACT | NC | RAM-RO-P |
0x1F | LightSourceThermalShutdownCounter | 0x00 | 0x00 | NVM-RO-P |
0x20 | LightSourceTemperature | ACT | NC | RAM-RO-P |
4.13 Memory Bank 207(luminaire maintenance data)
Address | Description | Default value | Reset value | Memory type |
0x00 | Address of last addressable memory location | 0x07 | NC | ROM |
0x01 | Reserved – not implemented | NO | NA | NA |
0x02 | Lock byte | 0xFF | 0xFF | RAM |
0x03 | Version of the memory bank | 0x01 | NC | ROM |
0x04 | RatedMedianUsefulLifeOfLuminaire | 0xFF | NC | NVM-P |
0x05 | InternalControlGearReferenceTemperature | 0xFF | NC | NVM-P |
0x06-0x07 | RatedMedianUsefulLightSourceStarts | 0xFF | NC | NVM-P |
5. Revision History
Date | Version | Changes |
2021.12.20 | 1.0 | Initial draft release |
2022.1.22 | 1.1 |
3. Change OEM Key to Master Key/User Key, rather than fixed key
4.1 All user to use left locations of MB0
4.3 Suppport PushDim operating mode
4.5 Add feature support: PHY, emergency, OTP
4.7 MB10 layout update to version 9
|
2022.1.25 | 1.2 | 4.2 Allow to use left locations of MB1 for OEM information |
2022.3.8 | 1.3 |
4 Change Gear to MB4, PushDim to MB2
4.4 Add Operating Time to MB3 CLO
4.5 Change Current Set location
4.7 Fix wrong bytes number of GTIN, add Command, support CLO Test mode. MB10 layout update to version 10
|
2023.8.16 | 1.4 |
4.1 Remove MB0 user additional information. Add build version, bootloader version
4.3 Remove PushDim operating mode in MB2. Add corridor parameters. Update MB2 layout to ver 2.
4.4 Update CLO layout to ver 2.
4.5 Update Gear layout to ver2. Support Emergency CCT.
4.6 Update MB10 to ver 11
|
2024.4.1 | 1.5 |
4.7 Change GTIN/ID/Hardware ver location on MB10. Update layout version to 12
|